Exemplary embodiments of the present invention relate to a semiconductor memory device, and more particularly, to a test operation of a synchronous semiconductor memory device.
As a manufacturing process and a design technology of semiconductor memory devices develop, the semiconductor memory devices can have comparatively large memory capacity. Also, the semiconductor memory devices can increase its operating speed. For instance, a synchronous semiconductor memory device is developed to match its data accessing speed with an operating speed of a system which it belongs to. As the synchronous semiconductor memory device inputs/outputs data in synchronization with a system clock, provided by the system, such as a central processing unit, its operating speed also increases.
The synchronous semiconductor memory device inputs pulse type command signals. The synchronous semiconductor memory device decodes inputted command signals to perform internally predetermined operations in response to decoded signals. The synchronous semiconductor memory device generally inputs the command signals, such as a chip selecting signal /CS, a column address strobe (CAS) signal /CAS, a row address strobe (RAS) signal /RAS, a write enable signal /WE, a clock enable signal CKE, and a clock signal CLK.
As the data accessing speed of the synchronous semiconductor memory device increases and it has larger memory capacity, a test operation for testing the synchronous semiconductor memory device becomes more critical. Some synchronous semiconductor memory devices recently developed perform a test operation under plural restrictions. For instance, all banks of the synchronous semiconductor memory device must be in a pre-charge mode to enter a test mode. Accordingly, there is a need to develop a synchronous semiconductor memory device capable of performing a test operation in any operation mode.